Embodiments of the present invention relate to a conductive lithographic polymer and method of making interconnection and conductive features for devices incorporating the conductive lithographic polymer.
An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor. Devices which may be formed within the semiconductor include transistors, bipolar transistors, diodes and diffused resistors, to name a few. Devices which may be formed within the dielectric include thin-film resistors and capacitors. Silicon or silicon comprising material is typically used as the substrate for these devices.
Typically, more than 100 integrated circuit die (IC chips) are constructed on a single 8-inch diameter silicon wafer. The devices are interconnected by conductor paths (also referred to as metalization layer) formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. In current practice, metalization layers, typically made of copper, are formed on dielectric layers to establish the conductor paths. Examples of processing methods to form the metalization layers include chemical vapor deposition (CVD), physical vapor deposition (PVD), and electrochemical deposition. Electrochemical deposition of copper has been found to provide the most cost-effective manner in which to deposit a copper metalization layer. In addition to being economically viable, such deposition techniques provide substantially conformal copper films that are mechanically and electrically suitable for interconnect structures.
An example of an electrochemical deposition is described (FIGS. 1A-1E). First, an electroless copper plated layer 102 is formed on an insulating layer 104 of a substrate 106, which may include thereon conductive features or devices 108 (FIG. 1A). The insulating layer 104 includes through holes or vias 110 to enable connection to the conductive features 108. The insulating layer 104 is typically an insulating layer which is interposed between conductor patterns formed on multiple layers for the purpose of ensuring the electrical insulation between the conductor patterns.
Next, a layer of photoresist layer 112 is patterned on the electroless copper plated layer 102 as shown in FIG. 1B. Next, an electrolytic copper plated layer 114 is formed on the exposed electroless copper plated layer 102 as shown in FIG. 1C. The electroless copper plated layer 102 is used as an electrical feed or seed layer for the electrolytic plating layer 114.
Next, the photoresist layer 112 is removed as shown in FIG. 1D. Next, the exposed electroless copper plated layer 102 is removed as shown in FIG. 1E by using a copper etching solution. Typically, an alkali etching solution is used as the etching solution. Due to the foregoing, a conductor pattern 116, in which the electrolytic copper plated layer 114 is laminated on the electroless copper plated layer 102, can be formed on the insulating layer 104. This process is typically repeated over and over for a formation of a multilayered device.
The current practice causes devices (e.g., printed circuit boards) to be fabricated with a long process throughput time because of the time consuming for film lamination to complete the patterning of the conductive layers. Layers of photoresist need to be used, layers of electroless plating and electrolytic plating have to be used, and removed at each step. In addition, various control systems are needed for chemical solutions to maintain line stability, for instance, in electroless plating process there is a need to control accurately and carefully the amount to be deposited and as well as controlling the thickness of the electroless plating. The fabrication process for devices thus becomes time consuming and costly.